The present invention relates to a manufacturing method of semiconductor devices each having a single layer or multilayer of polycrystalline silicon doped with impurity.
It is known that polycrystalline silicon with doped impurity is used as gates or internal wiring in MOS IC or LSI. It is for this reason that, in manufacturing MOS FET's, for example, the natures of low conductivity, good thermal resistivity and easy processing of such the polycrystalline silicon enable source, drain and gate to be self-aligned. At the initial stage of development of MOS IC and LSI using such the polycrystalline silicon, a single layer of the polycrystalline silicon was used; however, multilayers of the polycrystalline silicon have been increasingly used recently, in order to improve the integration density of the circuits.
Reference will be made to FIGS. 1A to 1C illustrating conventional devices with double layers or polycrystalline silicon including doped impurity.
FIG. 1A shows a cross sectional view of an overlapping type charge coupled device in which the transfer electrodes made of two layer of polycrystalline silicon with doped impurity are partly overlapped in disposition. As shown in FIG. 1A, first gate oxide layers 2a, 2b and 2c and second gate oxide layers 3a and 3b are provided on a substrate 1 of p-type single crystalline silicon. First polycrystalline silicon electrodes 4a, 4b and 4c each doped with impurity are formed on the first gate oxide layers 2a, 2b and 2c. Second polycrystalline silicon layers 5a and 5b each doped with impurity on the second gate oxide layers 3a and 3b. The first polycrystalline silicon electrodes 4a, 4b and 4c and the second polycrystalline silicon electrodes 5a and 5b are electrically insulated by an oxide layer 6 inserted therebetween.
FIG. 1B shows a cross sectional view of one cell of a transistor type dynamic random access memory having electrodes of the double layer polycrystalline silicon. The memory comprises storage elements each keeping charges therein representing logical "1" or "0" and transistors serving each as a switching element for transfer the charges stored in the storage element to the corresponding bit line for detection. As shown in FIG. 1B, a first gate oxide layer 8 and a second gate oxide layer 9 are formed on a p-type silicon monocrystalline silicon substrate 7, for example. These layers are surrounded by field oxide layers 10a and 10b. A first polycrystalline silicon electrode 11 doped with impurity is provided on the first gate oxide layer 8. The first polycrystalline silicon electrode 11 constitutes an electrode for the storage element of the dynamic random access memory. A second polycrystalline silicon electrode 12 with doped impurity is formed on the second gate oxide layer 9. The second polycrystalline silicon electrode 12 constitutes a gate of the switching transistor of the dynamic random access memory. The first polycrystalline silicon electrode 11 and the second polycrystalline silicon electrode 12 are electrically insulated by an oxide layer 13. The second polycrystalline silicon electrode 12 is connected to a metal line 15 of, for example, aluminum serving as a word line.
FIG. 1C shows a cross sectional view of one cell of an avalanche injection MOS memory of double polycrystalline silicon layers type. As shown in FIG. 1C, a first gate oxide layer 17 is formed on a p-type silicon monocrystalline silicon substrate 16, with a first polycrystalline silicon electrode 18 of a floating gate further formed on the first gate oxide layer 17. A second polycrystalline silicon electrode 20 is formed on the first polycrystalline silicon electrode 18 with an oxide layer 19 inserted therebetween for electrical insulation. The second polycrystalline silicon electrode 20 serves as a control gate. These first and second polycrystalline silicon electrodes are both doped with impurity. A source and a drain diffusion layers 21a and 21b are formed in the surface layer of the substrate 16, being disposed on both the lower sides of the first polycrystalline silicon electrode 18.
In the above-mentioned three devices with doped polysilicon double layers, the interface between the first and second (although not shown in FIG. 1C) gate oxide layers and the substrate, and its vicinity must be well conditioned physically and electrically. As a matter of course, there are many other examples of the device with polycrystalline silicon double layers, in addition to the above enumerated ones.
The explanation to follow with reference to FIGS. 2A to 2E is a conventional manufacturing method of the FIG. 1A device.
As shown in FIG. 2A, to start, a first gate oxide layer 23 is formed on a p-type monocrystalline silicon layer 22, for example. Then, the entire surface of the first gate oxide layer 23 is covered with a polycrystalline silicon layer 24. Into this polycrystalline silicon layer 24, a dopant, such as phosphorus or boron, is diffused to reduce the conductivity of the polycrystalline silicon layer 24. At the next step, photoresist layers 25a, 25b and 25c are patterned, by the photolithography, on the polycrystalline silicon layer 24 corresponding to the first polycrystalline silicon electrodes 4a, 4b and 4c shown in FIG. 1A. As shown in FIG. 2B, the polycrystalline silicon layer 24 is not covered with the photoresist layers is removed by, for example, the plasma etching method, using the photoresist layers 25a, 25b and 25c as an etching mask. This step forms first polycrystalline silicon electrodes 26a, 26b and 26c. After removal of the photoresist layers 25a, 25b and 25c, the first gate oxide layer 23 is removed by the oxide etching method using, for example, ammonium fluoride (NH.sub.4 F), with the etching mask of the first polycrystalline silicon electrodes 26a, 26b and 26c, as shown in FIG. 2C. This removal step is conducted leaving only the first gate oxide layers 27a, 27b and 27c under the first polycrystalline silicon electrodes 26a, 26b and 26c. Following this, the device thus far fabricated is thermal-oxided in a high temperature oxide atmosphere, with the result that the second gate oxide layers 28a, 28b and 28c are formed on the substrate 22 and oxide layers 29a, 29b and 29c are formed on the first polycrystalline silicon electrodes 26a, 26b and 26c. See FIG. 2D. Then, as in the step for forming the first polycrystalline silicon electrodes 26a, 26b and 26c, second polycrystalline silicon electrodes 30a, 30b and 30c are formed.
The conventional manufacturing method of the overlapping type charge coupled device with polycrystalline silicon double layers doped with impurity. Thus far described, however, is problematic in the step for manufacturing the second gate oxide layers 28a, 28b and 28c. The formation of the second gate oxide layers 28a, 28b and 28c is conducted through the oxidation in a high temperature oxide atmosphere in a state that the surfaces of the first polycrystalline silicon electrodes 26a, 26b and 26c and some portions of the substrate 22 surface are exposed. In this case, at the initial stage of the oxidation in the high temperature oxide atmosphere, the doped impurity is evaporated from the first polycrystalline silicon electrodes 26a, 26b and 26c, and sticks onto the exposed surface of the substrate 22 or the wall of an oxidation tube. The impurity stuck to the surface of the substrate 22, then, is diffused into the substrate by heating, so that it changes the inversion voltage of the MOS capacitor thereat. The impurity attached onto the wall of the oxidation tube is evaporated again to attach onto the substrate surface and a similar process is repeated to the substrate, with similar results.
Such the evaporation, attaching and diffusion of impurity when the random access memory as shown in FIG. 1B is manufactured, cause the threshold voltage of the switching transistor to change. The phenomena also cause change of the threshold voltages of the MOS FET's in the elements or circuits shown in FIGS. 1A to 1C or in the periphery circuits formed on the same substrate. The phenomena take place not entirely but locally on the exposure surfaces of the substrate 22, with an unsettled amount of evaporation and attaching of impurity. The variation of the threshold voltage of the MOS FET's deteriorates the yield of manufacturing the components or circuits including such the MOS FET's and the reliability of them manufactured.